In this blog we would be implementing a 3-bit palindrome sequence detector in Verilog. The problem is quite straightforward where we need to detect a 3-bit palindrome sequence from a continuous stream of single bit inputs.
There are different ways this problem can be looked into and one of them could be to use a finite state machine to detect input patterns of 000, 010, 101 and 111. However, the state machine can get a bit complex and you may end up missing an arc which may cause your logic to not work as intended. Instead we can solve this using a 2-bit shift register, a counter and a comparator.
The 2-bit shift register would be used to hold the last two bits seen in the sequence and the counter would only be used to ensure the logic works when the circuit has seen at least three bits since the last time it was reset. Once we have the counters and shift registers working, we would just need to compare bit of the shift register with the incoming bit (x_i) and assert the palindrome output if they match.
Here is the verilog code which implements the above logic: