The other problem in the RTL Design Hackathon was to design a 'sticky' negative edge detector or an edge capture circuit. The term sticky implies that the output would continue to remain asserted once the negative edge on the input is seen.

The defined module in the problem had a 32-bit data given as input. The module had one 32-bit output which identified that a negative edge was detected on the corresponding input bit. Here is the module definition:

module edge_capture (
  input   wire        clk,
  input   wire        reset,

  input   wire [31:0] data_i,

  output  wire [31:0] edge_o

);

In order to implement this logic, we just need flops to store the last seen input data value and some combinational logic to detect the negative edge. The negative edge can be detected by an AND of the negated input data with the last seen input data. This would give us the output for the current cycle however, the output is expected to be sticky. This is achieved by storing the output in flops. This is it and the following verilog code implement this:

module edge_capture (
  input   wire        clk,
  input   wire        reset,

  input   wire [31:0] data_i,

  output  wire [31:0] edge_o

);

  logic [31:0] data_q;
  logic [31:0] edge_q;
  logic [31:0] data_next;

  // Flops for input data and for sticky output behavior
  always @(posedge clk or posedge reset)
    if (reset) begin
      data_q[31:0] <= 32'h0;
      edge_q[31:0] <= 32'h0;
    end else begin
      data_q[31:0] <= data_i[31:0];
      edge_q[31:0] <= data_next[31:0];
    end

  assign data_next[31:0] = (~data_i[31:0] & data_q[31:0]) |
                           (edge_q[31:0]);

  assign edge_o[31:0] = data_next[31:0];

endmodule